Design and Analysis of 8T CMOS SRAM cell
نویسنده
چکیده
This paper addresses to enhance the stability of8T SRAM bitcell by lowering its leakage power. Scaling down of process parameters such as supply voltage affects the Read ability and Write stability of the cell. As number of transistors on chip increases power dissipation also increases and as a result of this stability of the cell gets affected. This paper aims at reducing the leakage power and improving the static noise margin of the cell. Static Noise Margin (SNM) is defined as the maximum amount of noise that a circuit can withstand at its input without causing any change in its output. Cadence Virtuoso tool was used for simulation and simulations were done using 180nm technology model file.
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